There were two interesting bits of RAM-related news yesterday from the EET, one of which I’ll cover in a later post. The one I want to discuss now concerns a new embedded DRAM technology from IBM that was announced Monday. I actually couldn’t find anything about it onIBM’s website, so the only details I have are from theEET piece. Luckily it’s a pretty detailed writeup. Basically, IBM has found a way to use a special set of “writeback buffers” to cut the cycle time for an embedded DRAM access in half. You may be wondering what this means and why you should care, so I’ll try to explain. (The following brief rundown is simplified; for a fuller explanation of RAM-related concepts, see theArs Technica RAM Guide).
Conventional processor designs use SRAM for any on-die cache (i.e. L1, L2, etc.). SRAM is very fast and very simple, but it uses four to six transistors per memory cell (depending on the design). So SRAM cache takes up a lot of die real estate, and the more cache you have the bigger the die grows. This being the case, it’s no wonder that some makers of embedded cores (ARM and MIPS) intended for SOC applications are coming out withcacheless core designs.
DRAM, on the other hand, lets you use one transistor per cell to store a bit, so embedding it on the processor die and using it as cache seems like an ideal alternative to using SRAM. The problem is that since that one transistor functions like a capacitor that gets discharged when you read from it, you have to refresh the data in it after each read. This is done by refreshing an entire row of cells at once. All this refreshing ties up the DRAM for a some time, which means that you can’t access it again until it’s done with its chores and is ready to go again. It’s these “chores” that increase the time between memory accesses (roughly speaking, the “cycle time”) and thus make DRAM much slower than SRAM. Since speed is the whole point of an on-die cache, this slowness rules out DRAM as an on-die cache alternative to SRAM for the most part. I say for the most part, because you still find embedded DRAM used in various applications. I’m thinking specifically of the “scratchpad RAM” in thePS2’s design, for instance.
